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f ed l610q461 - 01 issue date : oct. 10, 2013 m l610q461 / ml610q462/ml610q463 8 - bit microcontroller with a built - in lcd driver general description this lsi is a high - performance 8 - bit cmos microcontroller into which peripheral circuits, such as synchronous serial port, uart , rc oscillation type a/d converter, and lcd driver, are incorporated around lapis semiconductor - original 8 - bit cpu nx - u8/100 . ML610Q461 operates in both high/low - speed mode and power - saving mode, it is most suitable for battery operated products. ML610Q461p/ml610q462p/ml610q463p support industrial temperature - 40 c to +85 c, are added to the product lineup. features ? cpu ? 8 - bit risc cpu (cpu name : nx - u8/100) ? instruction system : 16- bit instructions ? instruction set: transfer, arithmetic operations, comparison, logic operation s, multiplication / division , bit manipulations , bi t logic operations, jump, condi tional jump, call return stack manipulations, arithmetic shift, and so on ? on - chip debug function ? minimum instruction execution time 30.5 s (@32.768 khz system clock ) 2 s (@ 500khz system clock ) 0.5 s(@2mhz system clock) ? internal memory ? internal 16kbyte flash rom ( 8 k 16 bits ) (including unusable 1k byte test area) ? internal 1kbyte data ram ( 1024 8 bits ) ? interrupt controller ? 1 non - maskable interrupt sources internal source: 1 (watch dog timer) ? 17 maskable interrupt sources internal sour ces: 12 (ssio0, timer0, timer1, timer2, timer3, uart0, rc - a/d converter, pwm0, tbc128hz, tbc32hz, tbc16hz, tbc2hz) external sources: 5 (p00, p01, p02, p03, p04) ? time base counter ? low - speed time base counter 1 ch annel f requency compensation ( compens ation range: approx. ? 488ppm to +488ppm . compensation accuracy : approx. 0.48ppm) ? high - speed time base counter 1 ch annel ? watchdog timer ? non - maskable interrupt and reset ? free running ? overflow period: 4 types selectable ( 125ms, 500ms, 2s, and 8s ) 1 / 34
f ed l610q461 - 01 ML610Q461 / m l 610q462/ml610q463 ? timer s ? 8 bits 4 ch annels ( timer0 - 3: 16- bit x 2 configuration available by using timer0 - 1 or timer2 - 3 ) ? clock frequency measurement mode (in one channel of 16 - bit configuration using timer2 - 3) ? capture ? time base capture 2 ch annels ( 4096 hz to 32 hz ) ? pwm ? resolution 16 bits 1 ch annel ? synchronous serial port ? master / slave selectable 1 ch annel ? lsb first /msb first selectable ? 8 - bit length /16 - bit length selectable ? uart ? half - duplex communication ? txd/rxd 1 ch annel ? bit length , parity/no parity, odd parity/even parity, 1 stop bit /2 stop bits ? positive logic / negative logic selectable ? built - in baud rate generator ? rc oscillation type a/d converter ? 16- bit counter ? time division 2 ch annels ? general - purpose ports ? input - only port 5 ch annels ( including secondary functions ) ? output - only port ML610Q461 : 10 ch annels ( including secondary functions ) ml610q462 : 6 ch annels ( including secondary functions ) ml610q463 : 2 ch annels ( including secondary functions ) ? input/output port 14 ch annels ( including secondary functions ) ? lcd driver ? the number of segments ML610Q461 : 64 dots max. ( 16 seg 4 com) ml610q462 : 80 dots max. ( 20 seg 4 com) ml610q463 : 96 dots max. ( 24 seg 4 com) ? 1/1 to 1/ 4 duty ? 1/2, 1/3 bias ( built - in bias gen eration circuit ) ? frame frequency selecable: approx. 64hz, 73hz, 85hz, and 102hz ? bias voltage multiplying clock selectable (8 types ) ? lcd drive stop mode, lcd display mode, all lcds on mode, and all lcds off mode selectable ? reset ? reset through the rese t _n pin ? power - on reset generation when powered on ? reset when oscillation stop of the low - speed clock is detected ? reset by the watchdog timer (wdt) overflow ? clock ? low - speed clock: crystal oscillation (32.768 khz) (this lsi can not guarantee the operation withoug low - speed crystal oscillation clock) ? high - speed clock: built - in rc oscillation (500 khz , 2mhz ) 2 / 34
f ed l610q461 - 01 ML610Q461 / m l 610q462/ml610q463 ? power management ? halt mode : instruction execution by cpu is suspended ( peripheral circuits are in operating states ) . ? stop mode : stop of low - speed oscillation and high - speed oscillation ( operations of cpu and peripheral circuits are stopped. ) ? high - speed clock gear : the frequency of high - speed system clock can be changed by software (1/1 , 1/2 , 1/4 , 1/8 of the oscillation clock ) ? b lock control function : resets and completely turns circuits of unused peripherals off. ? shipment ? chip ML610Q461 - wa ml610q46 2 - wa ml610q46 3 - wa ml610q4 61p - wa ml610q4 62p - wa ml610q4 63p - wa ? 64- pin plastic tqfp ml610q4 61- xxxtbz0a al ml610q4 6 2 - xxxtbz0a al ml610q4 63- xxxtbz0a al ml610q4 61p - xxxtb0a al ml610q4 62p - xxxtb0a al ml610q4 63p - xxxtb0a al ml610q4 61- xxxtbz w a al ml610q4 62- xxxtbz w a al ml610q4 63- xxxtbz w a al ml610q4 61p - xxxtb w a al ml610q4 62p - xxxtb w a al ml610q4 63p - xxxtb w a al xxx: rom code number (xxx is nn n for blank product) q: mtp version p: wide range temperature version wa: chip tbz0a al : tqfp (au wire bonding), tb0a al : tqfp (au wire bonding) (p version), tbz waal : tqfp (cu wire bonding)., tb waal : tqfp (cu wire bonding) (p version) ? guaranteed operati ng range ? operating temperature : ? 20 c to + 70 c (p version: ?40 c to +85 c) ? operating voltage : v dd = 1. 25v to 3.6v 3 / 34
f ed l610q461 - 01 ML610Q461 / m l 610q462/ml610q463 block diagram block diagram of ML610Q461/ml610q462/ml610q463 figure 1 show the block diagram of the ml610 q461/ml610q462/ml610q463 . ?*? indicates the secondary or tertiary function of eac h port. figure 1 ml610q 461/ml610q462/ml610q463 block diagram program memory (flash) 16kbyte ram 1kbyte interrupt controller cpu (nx - u8/100) timing controller n ci c ntrtion dodr contror ntrtion itr c 1 d 8it ir 4 capture 2 gpio int 5 data - bus test0 reset_n osc xt0 xt1 lsclk* outclk* power v dd cd drir cd v 1 v 2 v 3 c1 c2 c dc 2 c c c 1 3 psw elr1 hz 3 lr ecsr1 hz 3 dsr/csr pc greg 0 15 v v dd v 1 di ritr 6 it c to c3 8 to 23 6161 8 to 2 6162 8 to 31 6163 p00 to p04 p20 to p21 p30 to p35 p40 to p47 ssio sck0* sin0* sout0* int 1 uart int 1 int 1 pwm rxd0* txd0* pwm0* test1_n p60 to p67 (ML610Q461) p60 to p63 (ml610q462) cs1* in1* rs1* rt1* 4 / 34
f ed l610q461 - 01 ML610Q461 / m l 610q462/ml610q463 pin configuration ML610Q461 tqfp64 pin layout note: the assignment of the p30 to p3 5 are not in order. figure 2 ML610Q461 tqfp64 pin configuratio n 12 1 2 3 4 5 6 7 8 9 11 42 43 44 45 46 47 48 26 25 24 23 10 14 13 16 15 p35 p33 59 p32 58 p34 57 p31 56 p30 55 p04 54 p03 53 p02 52 p01 51 p00 50 p21 49 p20 v ss p60 64 63 62 61 60 seg14 seg13 seg12 seg11 seg10 seg9 seg8 com3 com2 com1 com0 v l3 v l2 v l1 c2 c1 p61 p62 p63 p64 p65 p66 p67 seg23 seg22 seg21 seg20 seg19 seg1 8 seg17 seg16 seg15 29 28 27 32 31 30 18 17 21 20 19 22 33 34 35 36 37 38 39 40 41 p40 p41 p42 p43 p44 p45 p46 p47 v dd v ss v ddl xt0 xt1 reset_n test0 test1_n v pp 5 / 34
f ed l610q461 - 01 ML610Q461 / m l 610q462/ml610q463 ml610q462 tqfp64 pin layout note: the assignment of the p30 to p3 5 are not in order. figure 3 ml610q462 tqfp64 pin configuratio n 1 2 1 2 3 4 5 6 7 8 9 11 42 43 44 45 46 47 48 26 25 24 23 10 14 13 16 15 p 35 p 33 59 p 32 58 p 34 57 p 31 56 p 30 55 p 04 54 p 03 53 p 02 52 p 01 51 p 00 50 p 21 49 p20 v ss p60 64 63 62 61 60 seg 14 seg 13 seg 12 seg 11 seg1 0 seg 9 seg 8 com3 co m2 com1 com0 v l3 v l2 v 1 c2 c1 61 62 63 2 26 25 2 23 22 21 2 1 18 1 16 15 2 28 2 32 31 3 18 1 21 2 1 22 33 3 35 36 3 38 3 1 1 2 3 5 6 v dd v v dd 1 1 v 6 / 34
f ed l610q461 - 01 ML610Q461 / m l 610q462/ml610q463 ml610q463 tqfp64 pin layout note: the assignment of the p30 to p3 5 are not in order. figure 4 ml610q463 tqfp64 pin configuratio n 1 2 1 2 3 4 5 6 7 8 9 11 42 43 44 45 46 47 48 26 25 24 23 10 14 13 16 15 p 35 p 33 59 p 32 58 p 34 57 p 31 56 p 30 55 p 04 54 p 03 53 p 02 5 2 p 01 51 p 00 50 p 21 49 p20 v ss seg 31 64 63 62 61 60 seg 14 seg 13 seg 12 seg 11 seg1 0 seg 9 seg 8 com3 com2 com1 com0 v l3 v l2 v 1 c2 c1 3 2 28 2 26 25 2 23 22 21 2 1 18 1 16 15 2 28 2 32 31 3 18 1 21 2 1 22 33 3 35 36 3 38 3 1 1 2 3 5 6 v dd v v dd 1 1 v 7 / 34
f ed l610q461 - 01 ML610Q461 / m l 610q462/ml610q463 ML610Q461 chip pin layout & dimension p 4 0 1 v pp 6 4 17 c1 3 3 seg1 5 p 41 2 p 42 3 p 43 4 p 44 5 p 45 6 p 46 7 p 47 8 v dd 9 v ss 10 v ddl 1 1 xt0 1 2 xt1 1 3 reset_n 1 4 test0 1 5 test1_n 1 6 18 c 2 19 v l1 20 v l2 2 1 v l3 2 2 com0 2 3 com1 2 4 com2 2 5 com3 2 6 seg8 2 7 seg9 2 8 seg10 2 9 seg11 3 0 seg12 31 seg13 32 seg14 3 4 seg1 6 3 5 seg1 7 3 6 seg1 8 3 7 seg1 9 38 seg 20 3 9 seg 21 40 seg 22 41 seg 23 42 p67 43 p66 44 p65 45 p64 46 p63 47 p62 48 p61 p35 63 p33 62 p32 61 p34 60 p31 59 p30 58 p04 57 p03 56 p02 55 p01 54 p00 53 p21 52 p2 0 51 v ss 50 p60 49 2.1 mm 2.0 mm x y note: the assignment of the pads p30 to p35 are not in order. chip size: 2.10 mm 2.00 mm pad cou nt: 64 pins minimum pad pitch: 80 m pad aperture: 70 m 70 m chip thickness: 350 m voltage of the rear side of chip: v ss level. figure 5 ML610Q461 chip layout & dimension 8 / 34
f ed l610q461 - 01 ML610Q461 / m l 610q462/ml610q463 ml610q462 chip pin layout & dimension p 4 0 1 v pp 6 4 17 c1 3 3 seg1 5 p 41 2 p 42 3 p 43 4 p 44 5 p 45 6 p 46 7 p 47 8 v dd 9 v ss 10 v ddl 1 1 xt0 1 2 xt1 1 3 reset_n 1 4 test0 1 5 test1_n 1 6 18 c 2 19 v l1 20 v l2 2 1 v l3 2 2 com0 2 3 com1 2 4 com2 2 5 com3 2 6 seg8 2 7 seg9 2 8 seg10 2 9 seg11 3 0 seg12 31 seg13 32 seg14 3 4 seg1 6 3 5 seg1 7 3 6 seg1 8 3 7 seg1 9 38 seg 20 3 9 seg 21 40 seg 22 41 seg 23 42 seg24 43 seg25 44 seg26 45 seg27 46 p63 47 p62 48 p61 p35 63 p33 62 p32 61 p34 60 p31 59 p30 58 p04 57 p03 56 p02 55 p01 54 p00 53 p21 52 p20 51 v ss 50 p60 49 2.1 mm 2.0 mm x y note: the ass ignment of the pads p30 to p35 are not in order. chip size: 2.10 mm 2.00 mm pad count: 64 pins minimum pad pitch: 80 m pad aperture: 70 m 70 m chip thickness: 350 m voltage of the rear side of chip: v ss level. figure 6 ml610q462 chip layout & dimensi on 9 / 34
f ed l610q461 - 01 ML610Q461 / m l 610q462/ml610q463 ml610q463 chip pin layout & dimension p 4 0 1 v pp 6 4 17 c1 3 3 seg1 5 p 41 2 p 42 3 p 43 4 p 44 5 p 45 6 p 46 7 p 47 8 v dd 9 v ss 10 v ddl 1 1 xt0 1 2 xt1 1 3 reset_n 1 4 test0 1 5 test1_n 1 6 18 c 2 19 v l1 20 v l2 2 1 v l3 2 2 com0 2 3 com1 2 4 com2 2 5 com3 2 6 seg8 2 7 seg9 2 8 seg10 2 9 seg11 3 0 seg12 31 seg13 32 seg14 3 4 seg1 6 3 5 seg1 7 3 6 seg1 8 3 7 seg1 9 38 seg 20 3 9 seg 21 40 seg 22 41 seg 23 42 seg24 43 seg25 44 seg26 45 seg27 46 seg28 47 seg29 48 seg30 p35 63 p33 62 p32 61 p34 60 p31 59 p30 58 p04 57 p03 56 p02 55 p01 54 p00 53 p21 52 p20 51 v ss 50 seg31 49 2.1 mm 2.0 mm x y note: the assignment of the pads p30 to p35 are not in order. chip size: 2.10 mm 2.00 mm pad count: 64 pins minimum pad pitch: 80 m pad aperture: 70 m 70 m chip thickness: 350 m voltage of the rear side of chip: v ss level. figure 7 ml610q463 chip layout & dimension 10/ 34
f ed l610q461 - 01 ML610Q461 / m l 610q462/ml610q463 ML610Q461/ml610q462/ml610q463 pad coordinates ta bl e 1 ml610 q461/ml610q462/ml610q463 pad coordinates chip center: x=0,y=0 pad no. pad name ml610 q 4 61/q462/q463 pad no. pad name ml610 q 4 61/q462/q463 x (m) y (m) x (m) y (m) (*1) pad for ML610Q461. (*2) pad for ml610q462. (*3) pad for ml610q463. 11/ 34
f ed l610q461 - 01 ML610Q461 / m l 610q462/ml610q463 pin list pin no. pad no. primary function s econdary function or tertiary function pin name i/o function secondary /tertiary pin name i/o function 10 50 10, 50 vss ? negative power supply pin ? ? ? ? 9 9 v dd ? ? ? ? ? ? power supply pin for internal logic (i nternally generated) ? ? ? ? 64 64 v pp ? ? ? ? ? ? power supply pin for lcd bias (internally generated or connected to positive power supply pin) (* 1 ) ? ? ? ? 20 20 v l2 ? power supply pin for lcd bias (internally generated or connected to positive power supply pin) (* 1 ) ? ? ? ? 21 21 v l3 ? power supply pin for lcd bias (internally generated) ? ? ? ? 17 17 c1 ? capacitor connection pin for lcd bias generation ? ? ? ? 18 18 c2 ? capacitor connection pin for lcd bia s generation ? ? ? ? 15 15 test0 i/o test pin ? ? ? ? 16 16 test1_n i test pin ? ? ? ? 14 14 reset_n i reset input pin ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 54 54 p01/exi1/ cap1 i input port, external interrupt, capture 1 input ? ? ? ? 55 55 p02/exi2/ rxd0 i input port, external interrupt, uart0 received data ? ? ? ? 56 56 p03/exi3 i input port, ex ternal interrupt ? ? ? ? 57 57 p04/exi4/ t02p0ck i input port, timer 0/timer 2/pwm0 external clock input external interrupt ? ? ? ? 51 51 p20/led0 o output port secondary lsclk o low - speed clock output 52 52 p21/led1 o output port secondary outclk o hig h - speed clock output 58 58 p30 i/o input/output port secondary in0 i rc type adc0 oscillation input pin 59 59 p31 i/o input/output port secondary cs0 o rc type adc0 reference capacitor connection pin 60 60 p34 i/o input/output port secondary rct0 o rc t ype adc0 resistor/capacitor sensor connection pin 61 61 p32 i/o input/output port secondary rs0 o rc type adc0 reference resistor connection pin 62 62 p33 i/o input/output port secondary rt0 o rc type adc0 measurement resistor sensor connection pin 63 6 3 p35 i/o input/output port secondary rcm o rc type adc oscillation monitor 12/ 34
f ed l610q461 - 01 ML610Q461 / m l 610q462/ml610q463 pin no. pad no. primary function secondary function or tertiary function pin name i/o function secondary /tertiary pin name i/o function 1 1 p40 i/o input/output port seconda ry ? ? ? ? ? ? 13/ 34
f ed l610q461 - 01 ML610Q461 / m l 610q462/ml610q463 pin no. pad no. primary function secondary functio n or tertiary function pin name i/o function secondary/ tertiary pin name i/o function 22 22 com0 o lcd common pin ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? (*1) internally generated, or connect to either positive power supply pin (v dd ) or power supply pin for internal logic (v ddl ). for details, see ?chapter 2 0 lcd drivers. i n the user ? s manual ? (*2) pad for ML610Q461. (*3) pad for ml610q462. (*4) pad for ml610q463. 14/ 34
f ed l610q461 - 01 ML610Q461 / m l 610q462/ml610q463 pin description pin name i/o description primary / s econdary/ tertiary logic system reset_n i reset input pin. when this pin is set to a ? l ? level, system reset mode is set and the internal section is initialized. when this pin is set to a ?h ? level subsequently, progr am execution starts. a pull - up resistor is internally connected. ? negative xt0 i crystal connection pin for low - speed clock. a 32.768 khz crystal oscillator ( see measuring circuit 1) is connected to this pin. capacitors cdl and cgl are connected across t his pin and v ss . ? ? xt1 o ? ? lsclk o low - speed clock output pin. this pin is used as the secondary function of the p20 pin. secondary ? outclk o high - speed clock output pin. this pin is used as the secondary function of the p2 1 pin. secondary ? ge neral - purpose input port p00 -p0 4 i general - purpose input port. since these pins have secondary functions, the pins cannot be used as a port when the secondary functions are used. primary positive general - purpose output port p2 0 - p21 o general - purpose out put port. since these pins have secondary functions, the pins cannot be used as a port when the secondary functions are used. primary positive general - purpose input/output port p3 0 - p35 i/o general - purpose input/output port. since these pins have secondar y functions, the pins cannot be used as a port when the secondary functions are used. primary positive p4 0 - p47 i/o general - purpose input/output port. since these pins have secondary functions, the pins cannot be used as a port when the secondary functions are used. primary positive p60 - p63 o general - purpose output port incorporated only into ML610Q461/ml610q462, and not into ml610q463. primary positive p64 - p67 o general - purpose output port incorporated only into ML610Q461, and not into ml610q462/ ml610q4 63. primary positive 15/ 34
f ed l610q461 - 01 ML610Q461 / m l 610q462/ml610q463 pin name i/o description primary / secondary/ tertiary logic uart txd0 o uart data output pin. this pin is used as the secondary function of the p 43 pin. secondary positive rxd0 i uart data input pin. this pin is used as the sec ondary function of the p42 or the primary function of the p02 pin. primary/ secondary positive synchronous serial (ssio) sck0 i/o synchronous serial clock input/output pin. this pin is used as the tertiary function of the p4 1 or p45 pin. tertiary ? sin0 i synchronous serial data input pin. this pin is used as the tertiary function of the p4 0 or p44pin. tertiary positive sout0 o synchronous serial data output pin. this pin is used as the tertiary function of the p4 2 or p46 pin. tertiary positive pwm pw m0 o pwm0 output pin. this pin is used as the tertiary function of the p43 or p34 pin. tertiary positive external interrupt exi 0 -4 i external maskable interrupt input pins. interrupt enable and edge selection can be performed for each bit by software. th ese pins are used as the primary functions of the p0 0 - p04 pins. primary positive/ negative capture cap0 i capture trigger input pins. the value of the time base counter is captured in the register synchronously with the interrupt edge selected by softwar e. these pins are used as the primary functions of the p0 0 pin(cap0) and p01 pin(cap1). primary positive/ negative cap1 i primary positive/ negative led drive led0 - 1 o n ch open drain output pins to drive led . primary positive/ negative 16/ 34
f ed l610q461 - 01 ML610Q461 / m l 610q462/ml610q463 pin name i/o description primary / secondary/ tertiary logic rc oscillation type a/d converter in0 i channel 0 oscillation input pin. this pin is used as the secondary function of the p30 pin. secondary ? cs0 o channel 0 reference capacitor connection pin. this pin i s used as the secondary function of the p3 1 pin. secondary ? r c t0 o resistor/capacitor sensor connection pin of channel 0 for measurement. this pin is used as the secondary function of the p3 3 pin. secondary ? rs0 o this pin is used as the secondary func tion of the p3 2 pin which is the reference resistor connection pin of channel 0. secondary ? rt0 o resistor sensor connection pin of channel 0 for measurement. this pin is used as the secondary function of the p3 4 pin. secondary ? rcm o rc oscillation mo nitor pin. this pin is used as the secondary function of the p3 5 pin. secondary ? in1 i oscillation input pin of channel 1 . this pin is used as the secondary function of the p44 pin. secondary ? cs1 o reference capacitor connection pin of channel 1 . this pin is used as the secondary function of the p4 5 pin. secondary ? rs1 o reference resistor connection pin of channel 1 . this pin is used as the secondary function of the p4 6 pin. secondary ? rt1 o resistor sensor connection pin for measurement of channe l 1 . this pin is used as the secondary function of the p4 7 pin. secondary ? lcd drive signal com 0 - 3 o common output pins. ? ? seg8 - 23 o segment output pins. ? ? seg24 -27 o segment output pins. incorporated into ml610q462/ml610q463, not into ML610Q461. ? ? seg28 - 31 o segment output pins. incorporated into ml610q463, not into ML610Q461/ml610q462. ? ? lcd driver power supply v l1 ? power supply pins for lcd bias ( internally generated or positive power supply pin connected ). depending on lcd bias setting and v dd voltage level, v dd or v ddl or capacitor is connected. for details of the connection method, see user ? s manual . ? ? v l2 ? ? ? v l3 ? ? ? c 1 ? power supply pins for lcd bias ( internally generated ) . capacitors c 12 is connected between c 1 and c 2. ? ? c 2 ? ? ? for testing test 0 i/o input/output pin for testing. a pull - down resistor is internally connected. ? ? test 1_n i input pin for testing. a pull - up resistor is internally connected. ? ? power supply v ss ? negative power supply pin. ? ? v d d ? positive power supply pin for i/o, internal regulator, battery low detector, and power - on reset. ? ? v ddl ? positive power supply pin (internally generated) for internal logic. capacitor cl ( see measuring circuit 1) is connected between this pin and v ss . ? ? v pp ? power supply pin for programming flash rom. a pull - down resistor is internally connected. ? ? 17/ 34
f ed l610q461 - 01 ML610Q461 / m l 610q462/ml610q463 termination of unused pins table 2 shows methods of terminating the unused pins. table 2 termination of unused pins pin recommended pin term ination v pp open v l1 , v l2 , v l3 open c 1 , c 2 open reset_n open test 0 open test1_n open p00 to p0 4 v dd or v ss p20 to p2 1 open p30 to p35 open p40 to p4 7 open p60 to p67 open com0 to 3 open seg 8 to 31 open note: it is recommended to set the un used input ports and input/output ports to the inputs with pull - down resistors/pull - up resistors or the output mode since the supply current may become excessively large if the pins are left open in the high impedance input setting. 18/ 34
f ed l610q461 - 01 ML610Q461 / m l 610q462/ml610q463 electrical character istics absolute maximum rating s (v ss = 0v ) parameter symbol condition rating unit power supply voltage 1 v dd ta = 25 c 0.3 to +4.6 v power supply voltage 2 v pp ta = 25 q c 0.3 to + 9 .5 v power supply voltage 3 v ddl ta = 25c ? 0.3 to + 3 .6 v power supply voltage 4 v l 1 ta = 25c ? 0.3 to + 2.0 v power supply voltage 5 v l 2 ta = 25 c 0.3 to + 4.0 v power supply voltage 6 v l 3 ta = 25 q c 0.3 to + 6.0 v input voltage v in ta = 25c ? 0.3 to v dd +0.3 v output voltage v out ta = 25c ? 0.3 to v dd +0.3 v output current 1 i out1 port 3 ? 6 , ta = 25 c 12 to +11 ma output current 2 i out2 port 2 , ta = 25 q c 12 to +20 ma power dissipation pd t a = 25c 0.9 w storage temperature t stg ? ? 55 to +150 c r ecommended operating conditions (v ss = 0v ) parameter symbol condition range unit operating temperature t op non - p version ? c p version ? 1. 25 to 3.6 v f op = 30k to 2.5mhz 1.8 to 3.6 operating frequency (cpu) f op v dd = 1. 25 to 3.6 v 30k to 625 k hz v dd = 1.8 to 3.6 v 30k to 2.5m low - speed crystal oscillation frequency f xtl ? 32.768k hz low - speed crystal oscillation external capacitor c dl ? ? ? 0.47 30% f capacitors externally connected to v l1, 2, 3 pins c a, b, c ? 0.1 30% f capacitors externally connected across c1 and c2 pins c 12 ? 0.47 30% f 19/ 34
f ed l610q461 - 01 ML610Q461 / m l 610q462/ml610q463 o perating conditions of flash rom ( v ss = 0v ) parameter symbol condition range unit operating temperature t op at write/erase 0 to +40 c operating voltage v dd at write/erase *1 2.75 to 3.6 v v dd l at write/erase *1 2.5 to 2.75 v pp at write/erase *1 7.7 t o 8.3 erase/program cyc l es c ep ? ? dc characteristics (1 /5 ) ( v dd = 1.25 to 3.6v , v ss = 0v , ta = ? 20 to +70 c , ta = ? 4 0 to + 85 c for p version, unless otherwise specified ) parameter symbol condition rating unit measuring circuit min. typ. max. 500khz/2mhz rc oscillation frequency f rc v dd = 1.25 to 3.6v ta = 25 c t yp. ? 10% 500 typ. + 10% khz 1 * 3 typ. ? 25% 500 typ. + 25% v dd = 1.80 to 3.6v ta = 25 c typ. ? 10% 2.0 typ. + 10% mhz * 3 typ. ? 25% 2.0 typ. + 25% low - speed crystal oscillation start time* 2 t xt l ? ? 0.6 2 s 500khz/2mhz rc oscillation start time t rc ? ? ? 0.3 s low - speed oscillation stop detect time *1 t stop ? 12 16.4 41 ms reset pulse width p rst ? ? ? s reset noise elimination pulse width p nrst ? ? ? 0.3 power - on reset activation power rise time t por ? ? ? 10 ms * 1 : when low - spee d crystal oscillation stops for a duration more than the low - speed oscillation stop detect time, the system is reset to shift to system reset mode. * 2 : use 32.768khz crystal resonator dt - 26 (load capacitance 6pf) ( made by kds:daishinku corp.) is used (c gl = c dl = 12 pf). * 3 : recommended o perating temperature ( ta = ? 2 0 to + 70 q c , ta = 4 0 to + 85 q c for p version) reset reset_n reset_n pin rese t vdd 0.9x v dd 0.1x v dd t por power on reset p rst vil1 vil1 20/ 34
f ed l610q461 - 01 ML610Q461 / m l 610q462/ml610q463 dc characteristics (2/ 5 ) ( v dd = 1.25 to 3.6v , v ss = 0v , ta = ? 20 to +70 c , ta = ? 4 0 to + 85 c for p version, unless otherwise sp ecified ) parameter symbol condition rating unit measuring circuit min. typ. max. v ddl voltage v ddl f op = 30k to 625 k hz 1.1 1.2 1.3 1 f op = 30k to 2.5mhz 1.35 1.5 1.65 v ddl temperature deviation * 1 ? v ddl v dd = 3.0v ? -1 ? mv/ c v ddl voltage dependency * 1 ? v ddl ? ? 5 20 mv/v * 1 : v ddl can not exceed v dd level. the maximum v ddl becomes v dd level when the v ddl calculated by the temperature deviation and voltage dependency is going to exceed the v dd level. 21/ 34
f ed l610q461 - 01 ML610Q461 / m l 610q462/ml610q463 dc characteristics ( 3/ 5 ) ( v dd = 3. 0 v , v ss = 0v , ta = ? 20 to +70 c , ta = ? 4 0 to + 85 c for p version ) parameter symbol condition rating unit measuring circuit min. typ. max. supply current 1 idd1 cpu : in stop state. low - speed/high- speed rc500khz/2mhz oscillation: stopped. ta = 25 c ? 0. 4 0.8 a 1 * 5 ? ? 8 supply current 2 idd2 cpu : in halt state (ltbc and wdt are operating). * 3 * 4 high - speed 500khz/2mhz oscillation: stopped. lcd and bias circuits: operating. * 6 ta = 25 c ? 0.9 1.8 a * 5 ? ? 9 supply current 3 idd3 cpu : in 32. 768khz operating state.* 1 * 3 high - speed 500khz/2mhz oscillation: stopped. lcd and bias circuits: operating. * 2 ta = 25 c ? 5 8 a * 5 ? ? 15 supply current 4 -1 idd4 -1 cpu : in rc 500 khz operating state. lcd and bias circuits: operating. * 2 ta = 25 c ? 7 0 100 a * 5 ? ? 120 supply current 4 -2 idd4 -2 cpu : in rc 2m hz operating state. lcd and bias circuits: operating. * 2 ta = 25 c ? 280 350 a * 5 ? ? 400 * 1 : when the cpu operating rate is 100% (no halt state). * 2 : all segs: off waveform, no lcd panel load, 1/3 bias, 1/3 duty, frame frequency: approx. 64 hz, bias voltage multiplying clock: 1/128 lsclk (256hz) * 3 : use 32.768khz crystal resonator dt - 26 (load capacitance 6pf) ( made by kds:daishinku corp. ) is used (c gl =c dl = 6 pf) * 4 : significant bits of blkcon0~blkcon4 registers except dlcd bit on blkcon4 are all ?1 ?. * 5 : recommended o perating temperature (ta = ? 2 0 to + 70 c , ta = ? 4 0 to + 85c for p version) * 6 : lcd stop mode, 1/3 bias, bias voltage multiplying clock: 1/128 lsclk (256hz) 22/ 34
f ed l610q461 - 01 ML610Q461 / m l 610q462/ml610q463 dc chara cteristics ( 4/ 5 ) ( v dd = 1.25 to 3.6v , v ss = 0v , ta = ? 20 to +70 c , ta = ? 4 0 to + 85 c for p version, unless otherwise specified ) parameter symbol condition rating unit measuring circuit min. typ. max. output voltage 1 ( p20 ? p21 nch open drain mode is not selected) (p30? p35) (p40? p47) (p60 ? p67) voh1 ioh1 = ? 0.5ma , v dd = 1.8 to 3.6v v dd ? ? ? v 2 ioh1 = - 0.03ma, v dd = 1.25 to 3.6v v dd ? ? ? vol1 iol1 = +0.5ma , v dd = 1.8 to 3.6v ? ? ? ? 0.3 out put voltage 2 ( p20 ? p21 nch open drain mode is selected) vol2 iol2 = +5ma , v dd = 1.8 to 3.6v ? ? 0.5 output voltage 3 (com0 ? 3) (seg8 ? 31) vo h3 io h4 = ? 0.05 ma , vl1=1.2v v l3 ? ? ? vo ml3 io mh4 = +0.05 ma , vl1=1.2v ? ? v l2 +0.2 vo ml3s io m4s = ? 0.05 m a , vl1=1.2v v l2 ? ? ? vo lm3 io ml4 = +0.05 ma , vl1=1.2v ? ? v l1 +0.2 vo lm3s io ml4s = ? 0.05 ma , vl1=1.2v v l1 ? ? ? vo l3 io l4 = +0.05 ma , vl1=1.2v ? ? 0.2 output leakage ( p20 ? p21) (p30? p35) (p40? p47) (p60 ? p67) iooh voh = v dd ( in high- impedan ce state ) ? ? 1 a 3 iool vol = v ss ( in high- impedance state ) ? 1 ? ? input current 1 ( reset _n, test1_n) ii h 1 vih 1 = v dd 0 ? 1 p a 4 iil1 vil 1 = v ss -600 -300 -2 input current 2 (test0) iih2 vih1 = v dd 2 300 ? ? ? ? 1 iil 3 z vil 3 = v ss ( in high- impedance state ) ? 1 ? ? 23/ 34
f ed l610q461 - 01 ML610Q461 / m l 610q462/ml610q463 dc characteristics (5/5) ( v dd = 1.25 to 3.6v , v ss = 0v , ta = ? 20 to +70 c , ta = ? 4 0 to + 85 c for p version, unless otherwise specified ) parameter symbol condition rating unit measuring circuit min. typ. max. input voltage 1 (re set _n) ( test 0, test1_n) ( p00 ? p0 4) (p30? p35) (p40? p47) vih 1 ? 0. 7 v dd ? v dd v 5 vil 1 v dd = 1.8 to 3.6v 0 ? 0. 3 0 ? 0. 2 c ? ? 5 p f ? 24/ 34
f ed l610q461 - 01 ML610Q461 / m l 610q462/ml610q463 m easuring circuits m easuring circuit 1 m easuring circuit 2 input pins v v dd v ddl v l1 v l2 v l3 v ss vih vil output pins (* 1 ) input logic circuit to determine the specified measuring conditions. ( * 2) measured at the specified output pins. (*2) (*1) c v : 1 f c a ,c b ,c c : 0. 1 f c 12 : 0.47 f 32.768khz crystal: dt - 26 (load capacitance 6pf) ( made by k ds:daishinku corp. ) c gl , c dl : 6pf xt0 xt1 a v dd v ddl c l v l1 c a v l2 v l3 c c v ss c2 c1 c 12 c v 32.768khz crystal c gl c dl 25/ 34
f ed l610q461 - 01 ML610Q461 / m l 610q462/ml610q463 m easuring circuit 3 m easuring circuit 4 m easuring circuit 5 input pins a v dd v ddl v l1 v l2 v l3 v ss output pins *3: measured at the specified output pins. (*3) input pins v dd v ddl v l1 v l2 v l3 v ss vih vil output pins * 1 : input logic circuit to determine the specified measuring conditions. (*1) waveform monitoring input pins a v dd v ddl v l2 v l3 v ss vih v l1 vil output pins * 1 : input logic circuit to determine the specified measuring conditions. *2: measured at the specified output pins. (*2) rs1 26/ 34
f ed l610q461 - 01 ML610Q461 / m l 610q462/ml610q463 ac charac teristics (external interrupt) ( v dd = 1.25 to 3.6v , v ss = 0v , ta = ? 20 to +70 c , ta = ? 4 0 to + 85 c for p version, unless otherwise specified ) parameter symbol condition rating unit min. typ. max. external interrupt disable period t nul interrupt: ena bled ( mie = 1 ), cpu : nop operation system clock : 32.768khz 76.8 ? 106.8 s ac characteristics (serial port) ( v dd = 1.25 to 3.6v , v ss = 0v , ta = ? 20 to +70 c , ta = ? 4 0 to + 85 c for p version, unless otherwise specified ) parameter symbo l condition rating unit min. typ. max. transmit baud rate t tbrt ? ? brt* 1 ? s receive baud rate t rbrt ? brt* 1 ? 27/ 34
f ed l610q461 - 01 ML610Q461 / m l 610q462/ml610q463 ac characteristics (synchronous serial port) ( v dd = 1.25 to 3.6v , v ss = 0v , ta = ? 20 to +70 c , ta = ? 4 0 to + 85 c for p version, unless otherwise specified ) parameter symbol c ondition rating unit min. typ. max. sclk n input cycle ( slave mode) t scyc when rc oscillation is 500khz * 2 ( v dd = 1.25 to 3.6v ) 10 ? ? s when rc oscillation is 2mhz * 3 ( v dd = 1.8 to 3.6v ) 2 ? ? sclk n output cycle ( master mode ) t scyc ? ? sclk n * 1 ? s sclk n input pulse width ( slave mode) t sw when rc oscillation is 500khz * 2 ( v dd = 1.25 to 3.6v ) 4 ? ? s when rc oscillation is 2mhz * 3 ( v dd = 1.8 to 3.6v ) 04 ? ? sclk n output pulse width ( master mode) t sw ? sclk n * 1 u 0.4 sclk n * 1 u 0.5 sclk n * 1 u 0.6 s sout n output delay time ( slave mode) t sd when rc oscillation is 500khz * 2 (v dd = 1.25 to 3.6v ) output load 10pf ? ? 500 ns when rc oscillation is 2mhz * 3 (v dd = 1.8 to 3.6v ) output load 10pf ? ? 240 sout n output delay time ( master mode) t sd when rc oscillation is 500khz * 2 (v dd = 1.25 to 3.6v ) output load 10pf ? ? 500 ns when rc oscillation is 2mhz * 3 (v dd = 1.8 to 3.6v ) output load 10pf ? ? 240 sin n input setup time ( slave mode ) t ss ? 80 ? ? ns sin n input setup time ( master mode) t ss when rc oscillation is 500khz * 2 ( v dd = 1.25 to 3.6v ) ? ? ns wh en rc oscillation is 2mhz * 3 ( v dd = 1.8 to 3.6v ) 240 ? ? sin n input hold time t sh when rc oscillation is 500khz * 2 ( v dd = 1.25 to 3.6v ) ? ? ns when rc oscillation is 2mhz * 3 ( v dd = 1.8 to 3.6v ) ? ? n= 0,1 *1: clock period selected with sn ck3 ? 0 of the serial port n mode register (s ion mod 1 ) * 2 : when 500khz rc oscillation is selected by oscm2 of the frequency control register ( fcon0 ) * 3 : when 2mhz rc oscillation is selected by oscm2 of the frequency control register ( fcon0 ) t sd sclkn* sinn* soutn* *: indicates the secondary function of the port (n= 0,1) t sd t ss t sh t sw t sw t scyc 28/ 34
f ed l610q461 - 01 ML610Q461 / m l 610q462/ml610q463 ac ch aracteristics (rc oscillation a/d converter) condition for v dd =1. 8 to 3.6v (v dd =1. 8 to 3.6v, v ss =0v, ta= - 20 to +70 c , ta= - 40 to +85 c for p v ersion, u nless otherwise specified ) parameter symbol condition rating unit min. typ. max. oscillation resi stor rs0,rs1,rt0, rt0 - 1,rt1 cs0, ct0, cs1 740pf 1 D D k ? oscillation frequency v dd = 3.0v f osc1 resistor for oscillation=1k ? 457.3 525.2 575.1 khz f osc2 resistor for oscillation=10k ? 53.48 58.18 62.43 khz f osc3 resistor for oscillation=100k ? 5.43 5.89 6.32 khz rs to rt oscillation frequency ratio *1 v dd = 3.0v kf1 rt0, rt0 - 1, rt1 =1k ? 7.972 9.028 9.782 ? kf2 rt0, rt0 - 1, rt1 =10k ? 0.981 1 1.019 ? kf3 rt0, rt0 - 1, rt1 =100k ? 0.099 0.101 0.104 ? * 1 : kfx is the ratio of the oscillation frequency by the sensor resistor to the oscillation freq uency by the reference resistor on the same conditions. kfx = f oscx (rt0 - cs0 oscillation) f oscx (rt0 - 1 - cs0 oscillation) f oscx (rt1 - cs1 oscillation) f oscx (rs0 - cs0 oscillation) , f oscx (rs0 - cs0 oscillation) , f oscx (rs1 - cs1 oscillation) ( x = 1, 2, 3 ) v d d v ddl c l v ss c v rcm frequency measurement (f oscx ) input pin vih vil 1 nt oi irit to dtrin t ifid rin ondition. cs0 rt0 cs0 rs0 rs0 rct0 rt0 - 1 ct0 rt0 in0 cvr0 (note 1) rt0, rt0 - 1, rt1: 1k @ /10k @ /100k @ rs0, rs1: 10 k @ cs0, ct0, cs1: 560pf cvr0, cvr1: 820pf in1 cs1 rs1 rt1 cs1 rs1 rt1 cvr1 29/ 34
f ed l610q461 - 01 ML610Q461 / m l 610q462/ml610q463 c ondition for v dd =1. 25 to 3.6v (v dd =1. 25 to 3.6v, v ss =0v, ta= - 20 to +70 c , ta= - 40 to +85 c for p v ersion, u nless otherwise specified ) parameter symbol condition rating unit min. typ. max. oscillati on resistor rs0,rs1,rt0, rt0 - 1,rt1 cs0, ct0, cs1 740pf 1 D D k ? oscillation frequency v dd = 1 . 5 v f osc1 resistor for oscillation= 6 k ? ? ? ? ? ? ? ? ? v dd = 3.0v f osc1 resistor f or oscillation= 6 k ? 85.28 94.58 103.3 khz f osc2 resistor for oscillation=1 5 k ? 35.72 38.87 41.78 khz f osc3 resistor for oscillation=10 5 k ? 5.189 5.622 6.012 khz rs to rt oscillation frequency ratio *1 v dd = 3.0v kf1 rt0, rt0 - 1, rt1 =1k ? 2.227 2.432 2.626 ? kf2 rt0, rt0 - 1, rt1 =10k ? 0.982 1 1.018 ? kf3 rt0, rt0 - 1, rt1 =100k ? 0.141 0.145 0.149 ? * 1 : kfx is the ratio of the oscillation frequency by the sensor resistor to the oscillation frequency by the reference resistor on the same conditions. kfx = f oscx (rt0 - cs0 oscillation) f oscx (rt0 - 1 - cs0 oscillation) f oscx (rt1 - cs1 oscillation) f oscx (rs0 - cs0 oscillation) , f oscx (rs0 - cs0 oscillation) , f oscx (rs1 - cs1 oscillation) ( x = 1, 2, 3 ) note : - please have the s hortest layout for the common node (wiring patterns which are connected to the external capacitors, resistors and in0/in1 pin), including cvr0/cvr1. especially, do not have long wire between in0/in1 and rs0/rs1. the coupling capacitance on the wires may oc cur incorrect a/d conversion. also, please do not have signals which may be a source of noise around the node. - when rt0/rt1 (thermistor and etc.) requires long wiring due to the restricted placement, please have vss(gnd) trace next to the signal. frequency measurement (f oscx ) nt in *1: input logic circuit to determine the specified measuring conditions. ot 1 v dd v ddl c l v ss c v rcm vih vil cs0 rt0 cs0 rs0 rs0 rct0 rt0 - 1 ct0 rt0 in0 cvr0 ra0 - 1 ra0 rt0, rt0 - 1, rt1: 1k @ /10k @ /100k @ ra0, ra0 - 1, ra1: 5k @ rs0, rs1: 15k @ cs0, ct0, cs1: 560pf cvr0, cvr1: 820pf in1 cs1 rs1 rt1 cs1 rs1 cvr1 ra1 rt1 30/ 34
f ed l610q461 - 01 ML610Q461 / m l 610q462/ml610q463 - pleas e make wiring to components (capacitor, resisteor and etc.) necessory for objective measurement. wiring to reserved components may affect to the a/d conversion operation by noise the components itself may have. 31/ 34
f ed l610q461 - 01 ML610Q461 / m l 610q462/ml610q463 package dimensions (unit : mm) notes fo r mounting the surface mount type package the surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. therefore, before you perform reflow mounting, contact our responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 32/ 34
f ed l610q461 - 01 ML610Q461 / m l 610q462/ml610q463 revision history document no. date page description previous edition current edition f edl610q46 1 - 01 oct . 10 ,201 3 ? ? final e dition 1 33/ 34
f ed l610q461 - 01 ML610Q461 / m l 610q462/ml610q463 n otes no copying or reproduction of this document, in part or in whole, is permitted without the consent of lapis semiconductor co., ltd. the content specified herein is subject to change for improvement without notice. examples of appli cation circuits, circuit constants and any other information contained herein illustrate the standard usage and operations of the products. the peripheral conditions must be taken into account when designing circuits for mass production. great care was tak en in ensuring the accuracy of the information specified in this document. however, should you incur any damage arising from any inaccuracy or misprint of such information, lapis semiconductor shall bear no responsibility for such damage. the technical inf ormation specified herein is intended only to show the typical functions of and examples of application circuits for the products. lapis semiconductor does not grant you, explicitly or implicitly, any license to use or exercise intellectual property or oth er rights held by lapis semiconductor and other parties. lapis semiconductor shall bear no responsibility whatsoever for any dispute arising from the use of such technical information. the products specified in this document are intended to be used with ge neral - use electronic equipment or devices (such as audio visual equipment, office - automation equipment, communication devices, electronic appliances and amusement devices). the products specified in this document are not designed to be radiation tolerant. while lapis semiconductor always makes efforts to enhance the quality and reliability of its products, a product may fail or malfunction for a variety of reasons. please be sure to implement in your equipment using the products safety measures to guard aga inst the possibility of physical injury, fire or any other damage caused in the event of the failure of any product, such as derating, redundancy, fire contro l and fail - safe designs. lapis semiconductor shall bear no responsibility whatsoever for your use of any product outside of the prescribed scope or not in accordance with the instruction manual. the products are not designed or manufactured to be used with any equipment, device or system which requires an extremely high level of reliability the failure or malfunction of which may result in a direct threat to human life or create a risk of human injury (such as a medical instrument, transportation equipment, aerospace machinery, nuclear - reactor controller, fuel - controller or other safety device). lapis s emiconductor shall bear no responsibility in any way for use of any of the products for the above special purposes. if a product is intended to be used for any such special purpose, please contact a rohm sales representativ e before purchasing. if you inten d to export or ship overseas any product or technology specified herein that may be controlled under the foreign exchange and the foreign trade law, you will be required to obtain a license or permit under the law. copyright 2013 lapis semiconductor co., ltd. 34/ 34

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